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32com/60seg driver & controller for dot matrix lcd S6A0071 1 introduction the S6A0071 is a dot matrix lcd controller & driver lsi which is fabricated by low power cmos technology. it can display 1 line 24 characters or 2 line 24 characters with 5 7 dots format. f un c tio n character type dot matrix single chip lcd controller & driver internal driver: 32 common and 60 segment signal output easy interface with 4 - bit or 8 - bit mpu display character pattern: 5 7 dots format (240 kinds) the special character pattern is programmable by character generator ra m directly. a customer character pattern is programmable by mask option. various instruction functions built - in automatic power on reset driving method is b - type (frame inversion) features internal memory character generator rom (cgrom): 8,400 bi ts (240 characters 5 7 dots) character generator ram (cgram): 64 8 bits (8 characters 5 8 dots) display data ram (ddram): 80 8 bits ( 80 characters max.) low power operation power supply voltage range (vdd): 2.4 to 5.5v lcd drive voltag e range (vdd - v5): 3.0 to 12.0v voltage doubler generates about double from signals power supply on chip generation of lcd supply voltage from voltage doubler (external supply also possible) programmable duty cycle 1/16 duty: 1 line 5 7 dots + curso r 24 characters 1/32 duty: 2 lines 5 7 dots + cursor 24 characters internal oscillator with an external resistor 118 t cp or b are chip available
S6A0071 32com/60seg driver & controller for dot matrix lcd 2 block diagram vdd gnd v1 v2 parallel/serial data conversion circuit busy flag character generator rom (cgrom) 8400 bits character generator ram (cgram) 512 bits cursor & blink controller circuit 5 5 input/ output buffer data register (dr) instruction register (ir) instruction decoder address counter (ac) display data ram (ddram) 640 bits timing generator circuit 32-bit shift register common driver 60-bit shift register 60-bit latch circuit seg- ment driver r/w rs e db0-db3 db4-db7 osc1 osc2 d seg1- seg60 com1- com32 8 8 8 8 7 8 7 8 8 7 32 60 v3 v4 v5 voltage doubler vci c1 c2 v5out t1 t2
32com/60seg driver & controller for dot matrix lcd S6A0071 3 pad diagram S6A0071 chip size: 3920 5080 pad size: 100 100 unit: m m (0, 0) x y seg45 1 seg46 2 seg47 3 seg48 4 seg49 5 seg50 6 seg51 7 seg52 8 seg53 9 seg54 10 seg55 11 seg56 12 seg57 13 seg58 14 seg59 15 seg60 16 com9 17 com10 18 com11 19 com12 20 com13 21 com14 22 com15 23 com16 24 com25 25 com26 26 com27 27 com28 28 com29 29 com30 30 com31 31 com32 32 vss 33 osc1 34 osc2 35 v1 36 v2 37 v3 38 v4 39 v5 40 v5out 41 c1 42 c2 43 vci 44 vdd 45 rs 46 r/w 47 e 48 db0 49 db1 50 db2 51 db3 52 db4 53 db5 54 db6 55 db7 56 t2 57 t1 58 90 seg16 89 seg15 88 seg14 87 seg13 86 seg12 85 seg11 84 seg10 83 seg9 82 seg8 81 seg7 80 seg6 79 seg5 78 seg4 77 seg3 76 seg2 75 seg1 74 com1 73 com2 72 com3 71 com4 70 com5 69 com6 68 com7 67 com8 66 com17 65 com18 64 com19 63 com20 62 com21 61 com22 60 com23 59 com24 118 seg44 117 seg43 116 seg42 115 seg41 114 seg40 113 seg39 112 seg38 111 seg37 110 seg36 109 seg35 108 seg34 107 seg33 106 seg32 105 seg31 104 seg30 103 seg29 102 seg28 101 seg27 100 seg26 99 seg25 98 seg24 97 seg23 96 seg22 95 seg21 94 seg20 93 seg19 92 seg18 91 seg17 note: " S6A0071" marking is to make the pad no. 95 easy to find.
S6A0071 32com/60seg driver & controller for dot matrix lcd 4 pad center coordinat es pad pad coordinate pad pad coordinate pad pad coordinate num. name x y num. name x y num. name x y 1 seg45 - 1794 2170 41 v5out - 562 - 2374 81 seg7 1794 910 2 seg46 - 1794 203 0 42 c1 - 438 - 2374 82 seg8 1794 1050 3 seg47 - 1794 1890 43 c2 - 312 - 2374 83 seg9 1794 1190 4 seg48 - 1794 1750 44 vci - 188 - 2374 84 seg10 1794 1330 5 seg49 - 1794 1610 45 vdd - 62 - 2374 85 seg11 1794 1470 6 seg50 - 1794 1470 46 rs 62 - 2374 86 seg12 1794 16 10 7 seg51 - 1794 1330 47 r/w 118 - 2374 87 seg13 1794 1750 8 seg52 - 1794 1190 48 e 312 - 2374 88 seg14 1794 1890 9 seg53 - 1794 1050 49 db0 438 - 2374 89 seg15 1794 2030 10 seg54 - 1794 910 50 db1 562 - 2374 90 seg16 1794 2170 11 seg55 - 1794 770 51 db2 688 - 2374 91 seg17 1686 2374 12 seg56 - 1794 630 52 db3 812 - 2374 92 seg18 1561 2374 13 seg57 - 1794 490 53 db4 938 - 2374 93 seg19 1436 2374 14 seg58 - 1794 350 54 db5 1062 - 2374 94 seg20 1311 2374 15 seg59 - 1794 210 55 db6 1188 - 2374 95 seg21 1186 2374 16 s eg60 - 1794 70 56 db7 1312 - 2374 96 seg22 1061 2374 17 com9 - 1794 - 70 57 t2 1438 - 2374 97 seg23 936 2374 18 com10 - 1794 - 210 58 t1 1562 - 2374 98 seg24 811 2374 19 com11 - 1794 - 350 59 com24 1794 - 2170 99 seg25 686 2374 20 com12 - 1794 - 490 60 com23 1794 - 2030 100 seg26 561 2374 21 com13 - 1794 - 630 61 com22 1794 - 1890 101 seg27 436 2374 22 com14 - 1794 - 770 62 com21 1794 - 1750 102 seg28 311 2374 23 com15 - 1794 - 910 63 com20 1794 - 1610 103 seg29 186 2374 24 com16 - 1794 - 1050 64 com19 1794 - 1470 104 seg30 61 2374 25 com25 - 1794 - 1190 65 com18 1794 - 1330 105 seg31 - 64 2374 26 com26 - 1794 - 1330 66 com17 1794 - 1190 106 seg32 - 189 2374 27 com27 - 1794 - 1470 67 com8 1794 - 1050 107 seg33 - 314 2374 28 com28 - 1794 - 1610 68 com7 1794 - 910 108 seg34 - 439 2374 29 com29 - 1794 - 1750 69 com6 1794 - 770 109 seg35 - 564 2374 30 com30 - 1794 - 1890 70 com5 1794 - 630 110 seg36 - 689 2374 31 com31 - 1794 - 2030 71 com4 1794 - 490 111 seg37 - 814 2374 32 com32 - 1794 - 2170 72 com3 1794 - 350 112 seg38 - 939 2374
32com/60seg driver & controller for dot matrix lcd S6A0071 5 pad center coordin ates (continued) pad pad coordinate pad pad coordinate pad pad coordinate num. name x y num. name x y num. name x y 33 vss - 1562 - 2374 73 com2 1794 - 210 113 seg39 - 1064 2374 34 osc1 - 1438 - 2374 74 com1 1794 - 70 114 seg40 - 1189 2374 35 osc2 - 1312 - 2374 75 seg1 1794 70 115 seg41 - 1314 2374 36 v1 - 1188 - 2374 76 seg2 1794 210 116 seg42 - 1439 2374 37 v2 - 1062 - 2374 77 seg3 1794 350 117 seg43 - 1564 2374 38 v3 - 938 - 2374 78 seg4 1794 490 118 seg44 - 1689 2374 39 v4 - 812 - 2374 79 seg5 1794 630 40 v5 - 68 8 - 2374 80 seg6 1794 770
S6A0071 32com/60seg driver & controller for dot matrix lcd 6 pad description pad ( no.) pad no. i/o name description interface v dd 45 for logical circuit (+3v, 5v) v ss 33 supply voltage ground (0v) power supply v1 - v5 36 - 40 bias voltage level for lcd driv ing s1 - s60 75 - 118, 1 - 16 o segment output segment signal output for lcd drive lcd c1 - c8 c9 - c16 c17 - c24 c25 - c32 74 - 67, 17 - 24, 66 - 59, 25 - 32, o common output common signal output for lcd drive lcd osc1 34 i oscillator when using internal oscillator, connec t external rf resistor. external resistor osc/osc2 osc2 35 o oscillator if external clock is used, connect it to osc1 external clock (osc1) rs 46 i register select used as register selection input. when rs = 1, data register is selected. when rs = 0, ins truction register is selected. mpu r/w 47 i read/write used as read/write selection input. when rw = 1, read operation. when rw = 0, write operation. mpu e 48 i read/write enable used as read/write enable signal. mpu db0 - db3 49 - 52 i/o data bus 0 - 7 in 8 - bit bus mode, used as low order bidirectional data bus. in 4 - bit bus mode, open these pins. mpu db4 - db7 53 - 56 i/o data bus 0 - 7 in 8 - bit bus mode, used as high order bidirectional data bus. in 4 - bit bus mode, used as both high and low order. db7 u sed for busy flag output. mpu vci 44 i voltage doubler output input terminal for voltage doubler. (normally vci = v dd ) power supply c1,c2 42, 43 i capacitor capacitor for voltage doubler connecting terminal (+). capacitor for voltage doubler connecting t erminal( - ). capacitor v5out 41 o voltage doubler output voltage doubler output terminal connected to lcd supply voltage v5 t1, t2 58, 57 i test pin maker testing terminal (normally open)
32com/60seg driver & controller for dot matrix lcd S6A0071 7 function description system interface this chip has both kinds of interface type with mpu: 4 - bit bus and 8 - bits bus. 4 - bit bus and 8 - bit bus are selected by the dl bit in the instruction register. during read or write operation, two 8 - bit registers are used. one is the data register (dr), and the other is the instruc tion register (ir). the data register (dr) is used as a temporary data storage place for being written into or read from ddraw/cgram . target ram is selected by ram address setting instruction. each internal operation, reading from or writing into ram, is done automatically. thus, after mpu reads dr data, the data in the next ddram/cgram address is transferred into dr automatically. also, after mpu writes data to dr, the data in dr is transferred into ddram/cgram automatically. the instruction register (ir) is used only to store instruction codes transferred from mpu. mpu cannot use it to read instruction data. to select a register, you can use the rs input pin in 4 - bit/8 - bit bus mode. table 1. various kinds of operations to rs and r/w b its rs r/w operation 0 0 instruction write operation (mpu writes instruction code into ir) 0 1 read busy flag (db7) and address counter (db0 - db7) 1 0 data write operation (mpu writes data into dr) 1 1 data read operation (mpu reads data into dr) busy flag (bf) when bf = 1, it indicates that the internal operation is being processed. so during this time the next instruction cannot be accepted. bf can be read through db7 port, when rs = 0, and r/w = 1. (read instruction operation). before executing the next instruction, be sure that bf is not 1. address counter (ac) the address counter (ac) stores ddram/cgram addresses, transferred from ir. after writing into (reading from) ddram/cgram. ac is automatically increased (decreased) by 1. when rs = 0 and r/w = 1, ac can be rea d through ports db0 - db6.
S6A0071 32com/60seg driver & controller for dot matrix lcd 8 display data ram (ddram) the ddram stores display data of maximum 80 8 bits (80 characteristics). the ddram address is set in the address counter (ac) as a hexadecimal number. (refer to fig - 1). ac6 msb lsb ac5 ac4 ac3 ac2 ac1 ac0 fi gure 1. ddram address 1) 1 - line d isplay in case of a 1 - line display, the address range of ddram is 00h - 04h. display position ddram address 00 1 com1 com8 01 02 03 04 05 06 07 2 3 4 5 6 7 8 seg1 S6A0071 seg60 08 9 09 0a 0b 0c 0d 0e 0f 10 11 12 13 14 15 16 10 17 11 12 13 14 15 16 17 18 19 20 21 22 23 24 seg1 S6A0071 seg60 08 1 com1 com8 01 02 03 04 05 06 07 2 3 4 5 6 7 8 10 9 09 0a 0b 0c 0d 0e 0f 10 11 12 13 14 15 16 18 17 11 12 13 14 15 16 17 18 19 20 21 22 23 24 00 1 com1 com8 01 02 03 04 05 06 07 2 3 4 5 6 7 8 08 9 09 0a 0b 0c 0d 0e 0f 10 11 12 13 14 15 16 10 17 11 12 13 14 15 16 18 19 20 21 22 23 24 (after shift left) (after shift right) 4f com9 com16 com9 com16 com9 com16 figure 2. 1 - line 24 char. display
32com/60seg driver & controller for dot matrix lcd S6A0071 9 2) 2 - line d isplay in case of a 2 - line display, the address range of ddram is 00h - 27h and 40h - 67h. display position ddram address 00 1 com1 com8 01 02 03 04 05 06 07 2 3 4 5 6 7 8 08 9 09 0a 0b 0c 0d 0e 0f 10 11 12 13 14 15 16 10 17 11 12 13 14 15 16 17 18 19 20 21 22 23 24 1 com1 com8 01 02 03 04 05 06 07 2 3 4 5 6 7 8 08 9 09 0a 0b 0c 0d 0e 0f 10 11 12 13 14 15 16 10 17 11 12 13 14 15 16 17 18 19 20 21 22 23 24 seg1 S6A0071 seg60 S6A0071 seg1 seg60 40 41 42 43 44 45 46 47 48 49 4a 4b 4c 4d 4e 4f 50 51 52 53 54 55 56 57 com17 com24 41 42 43 44 45 46 47 48 49 4a 4b 4c 4d 4e 4f 50 51 52 53 54 55 56 57 com17 com24 (after shift left) 00 1 com1 com8 01 02 03 04 05 06 07 2 3 4 5 6 7 8 08 9 09 0a 0b 0c 0d 0e 0f 10 11 12 13 14 15 16 10 17 11 12 13 14 15 16 18 19 20 21 22 23 24 40 41 42 43 44 45 46 47 48 49 4a 4b 4c 4d 4e 4f 50 51 52 53 54 55 56 com17 com24 (after shift right) 18 58 27 67 com9 com16 com25 com32 com9 com16 com25 com32 com9 com16 com25 com32 figure 3. 2 - line 24 char. display with 60 seg. extension driver
S6A0071 32com/60seg driver & controller for dot matrix lcd 10 cgrom (characteristic generator rom) cgrom has a 5 x 7 dots 240 character pattern. cgram (character generator ram) cdram has up to 5 x 8 dots 8 characters. by writing font data to cgram, user defined characters can be used (refer to table 3). timing generation circuit the timing generation circuit generates clock signals for the internal operations. lcd driver circuit lcd driver circuit has 32 common and 60 segment signals for lcd driving. data from cgram/cgrom is transferred to an 60 - bit segment latch serially, and then stored to an 60 - bit shift latch. when each com is selected by a 32 - bit common register, segment data is also outputs throu gh the segment driver from and 60 - bit segment latch. in case of a 1 - line display mode, com1 to com8 have 1/6 duty, and in 2 - line display mode, com1 to com32 have 1/32 duty ratio. cursor/blink control circuit it controls cursor/blink on/off at cursor positi on.
32com/60seg driver & controller for dot matrix lcd S6A0071 11 table 3. relationship between character code (ddram) and character pattern (cgrom) 0 1 1 0 0 1 1 1 0 d7 d6 d5 d4 d3 d2 d1 d0 a5 a4 a3 a2 a1 a0 p7 p6 p5 p4 p3 p2 p1 p0 character code (ddram data) cgram address cgram data pattern number 0 0 x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 . . . . . . . . . . 0 0 0 x 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 x x x 0 0 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 pattern 1 x x x 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 . . . . . . . . . . . . . . . . . . . . pattern 8 . . . . . . . . . . . . . . . . . . . . "x": d on't care .
S6A0071 32com/60seg driver & controller for dot matrix lcd 12 instruction descript ion outline to overcome the speed difference between internal clock of S6A0071 and mpu clock, s6a00 71 performs internal operation by storing control information to ir or dr. the internal operation is determined according to the signal from mpu, composed of read/write and data bus. (refer to table 5 ) instruction can be divided largely four kinds, (1) s 6a0071 function set instructions ( set display methods, set data length, etc.) (2) address set instructions to internal ram (3) data transfer instructions with internal ram (4) others. the address of internal ram is automatically increased or decrease d by 1. note: during internal operation, busy flag (db7) is read "1". busy flag check must be precede by the next instruction. when you make an mpu program with checking the busy flag (db7) is made, it must be necessary 1/2 fosc for executing the nex t instruction by falling e signal after the busy flag (db7) goes to "0". contents 1) clear display rs r/w db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 0 0 0 0 0 1 clear all the display data by writing "20h" (space code) to all ddram address, and set ddram address to "00h" into ac (address counter). return cursor to the original status, namely, bring the cursor to the left edge on first line of the display. make entry mode increment (i/d = "1"). 2) return home rs r/w db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 0 0 0 0 1 x * "x": don't care return home is cursor return home instruction. set ddram address to "00h" into the address counter. return cursor to its original site and return display to its original status, if shifted. contents of ddram does not change.
32com/60seg driver & controller for dot matrix lcd S6A0071 13 3) entry mode set rs r/w db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 0 0 0 1 i/d sh set the moving direction of cursor and display. i/d: increment / d ecrement of ddram a ddress ( c ursor or b link) when i/d = "1", cursor/blink moves to right and ddram addres s is increased by 1. when i/d = "0", cursor/blink moves to left and ddram address is decreased by 1. * cgram operates the same as ddram, when reading from or writing to cgram. sh: shift of e ntire d isplay when ddram is in the read (cgram read/write) oper ation or sh = "0", shift of entire display is not performed. if sh = "1" and ddram is in the write operation, shift of entire display is performed according to i/d value (i/d = "1" : shift left, i/d = "0" : shift right). 4) display on/off control rs r/w d b7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 0 0 1 d c b control display/cursor/blink on/off 1 bit register. d: display on/off c ontrol b it when d = "1", entire display is turned on. when d = "0", display is turned off, but display data remained in ddram. c: c ursor on/off c ontrol b it when c = "1", cursor is turned on. when c = "0", cursor is disappeared in current display, but i/d register preserves its data. b: cursor blink on/off c ontrol b it when b = "1", cursor blink is on, which performs alternate between a ll the "1" data and display character at the cursor position. when b = "0", blink is off.
S6A0071 32com/60seg driver & controller for dot matrix lcd 14 5) cursor or display shift rs r/w db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 0 1 s/c r/l x x without waiting or reading the display data, shift right/left cursor po sition or display. this instruction is used to correct or search display data (refer to table 6) . during 2 - line mode display, cursor moves to the 2nd line after the 40th digit of the 1st line. note that display shift is performed simultaneously for the who le line. when displayed data is shifted repeatedly, each line is shifts individually. when display shift is performed, the contents of the address counter are not changed. table 6. shift patterns according to s/c and r/l bits s/c r/l operation 0 0 shift c ursor to the left, ac is decreased by 1 0 1 shift cursor to the right, ac is increased by 1 1 0 shift all the display to the left, cursor moves according to the display 1 1 shift all the display to the right, cursor moves according to the display 6) f unction set rs r/w db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 1 dl n x x x dl: interface data length control bit when dl = "1", it means 8 - bit bus mode with mpu. when dl = "0", it means 4 - bit bus mode with mpu. hence, dl is a signal to select 8 - bit or 4 - bi t bus mode. when 4 - bit bus mode, it needs to transfer 4 - bit data by two times. n: display line number control bit when n = "0", it means 1 - line display mode. when n = "1", 2 - line display mode is set. 7) set cgram address rs r/w db7 db6 db5 db4 db3 db2 db 1 db0 0 0 0 1 ac5 ac4 ac3 ac2 ac1 ac0 set cgram address to ac. this instruction makes cgram data available from mpu.
32com/60seg driver & controller for dot matrix lcd S6A0071 15 8) set ddram address rs r/w db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 ac6 ac5 ac4 ac3 ac2 ac1 ac0 set ddram address to ac. this instruct ion makes ddram data available from mpu. when 1 - line display mode (n = 0), ddram address is from "00h" to "4fh". in 2 - line display mode (n = 1), ddram address in the 1st line is from "00h" to "27h", and ddram address in the 2nd line is from "40h" to "67h". 9) read busy flag & address rs r/w db7 db6 db5 db4 db3 db2 db1 db0 0 1 bf ac6 ac5 ac4 ac3 ac2 ac1 ac0 this instruction shows whether S6A0071 is in internal operation or not. if the resultant bf is "1", it means the internal operation is in progress and you have to wait until bf to be low, and then the next instruction can be performed. in this instruction you can read also the value of address counter. 10) write data to ram rs r/w db7 db6 db5 db4 db3 db2 db1 db0 1 0 d7 d6 d5 d4 d3 d2 d1 d0 write bina ry 8 - bit data to ddram/cgram. the selection of ram from ddram, and cgram, is set by the previous address set instruction: (ddram address set, cgram address set). ram set instruction can also determine the ac direction to ram. after write operation, the ad dress is automatically increased/decreased by 1, according to the entry mode. 11) read data from ram rs r/w db7 db6 db5 db4 db3 db2 db1 db0 1 1 d7 d6 d5 d4 d3 d2 d1 d0 read binary 8 - bit data from ddram/cgram. the selection of ram is set by the previous address set instruction. if the address set instruction of ram is not performed before this instruction, the data that is read first is invalid, because the direction of ac is not determined. if you read ram data several times without ram address set instr uction before read operation, you can get correct ram data from the second, but the first data would be incorrect, because there is no time margin to transfer ram data. in case of ddram read operation, cursor shift instruction plays the same role as ddram address set instruction; it also transfer ram data to output data register. after read operation address counter is automatically increased/decreased by 1 according to the entry mode. after cgram read operation, display shift may not be executed correctly. note: in case of ram write operation, ac is increased/decreased by 1 like read operation. in this time, ac indicates the next address position, but you can read only the previous data by read instruction.
S6A0071 32com/60seg driver & controller for dot matrix lcd 16 table 6. instruction table instruction instru ction code description execution rs r/ w db 7 db 6 db 5 db 4 db 3 db 2 db 1 db 0 instruction code time(fsoc=270 ) clear display 0 0 0 0 0 0 0 0 0 1 write "20h" to ddram. and set ddram address to "00h" from ac. 1.53ms return home 0 0 0 0 0 0 0 0 1 x set ddram add ress to "00h" from the ac and return cursor to its original position if shifted. the contents of ddram are not change. 1.53ms entry mode set 0 0 0 0 0 0 0 1 i/d sh assign cursor moving direction and make shift of entire display possible. 39 m s display on/off control 0 0 0 0 0 0 1 d c b set display(d), cursor(c), and blinking of cursor(b) on/off control bit. 39 m s cursor or display shift 0 0 0 0 0 1 s/c r/l x x set cursor moving and display shift control bit, and the direction, without chang ing of the ac. 39 m s function set 0 0 0 0 1 dl n x x x set interface data length (dl : 4 - bit/8 - bit), numbers of display line (n : 1 - line/2 - line). 39 m s set cgram address 0 0 0 1 ac5 ac4 ac3 ac2 ac1 ac0 set cgram address in address counter. 39 m s set ddram address 0 0 1 ac6 ac5 ac4 ac3 ac2 ac1 ac0 set ddram address in address counter. 39 m s read busy flag and address 0 1 bf ac6 ac5 ac4 ac3 ac2 ac1 ac0 whether during internal operation or not can be known by reading bf. the contents of address counter can al so be read. 0 m s write data to ram 1 0 d7 d6 d5 d4 d3 d2 d1 d0 write data into internal ram (ddram/cgram). 43 m s read data from ram 1 1 d7 d6 d5 d4 d3 d2 d1 d0 read data from internal ram (ddram/cgram). 43 m s *"x": don't care note: when you make an mpu program, checking the busy flag (db7), a time margin of 1/2 f osc is necessary for executing the next instruction by the falling edge of the 'e' signal after the busy flag (db7) goes to "0".
32com/60seg driver & controller for dot matrix lcd S6A0071 17 interface with mpu 1) interface with 8 - bit mpu when the int erfacing data length are 8 - bit, transfer is performed all at once through 8 ports, from db0 to db7. an example of the timing sequence is shown below. rs r/w e internal signal db7 internal operation data busy busy no busy data instruction busy flag check instruction busy flag check busy flag check figure 4. example of 8 - bit bus mode timing diagram 2) interface with 4 - bit m pu when interfacing data length is 4 - bit, only 4 ports, from db4 to db7, are used as data bus. at first higher 4 - bit (in the case of 8 - bit bus mode, the contents of db4 - db7), and then lower 4 - bit (in case of 8 - bit bus mode, the contents of db0 - db3) ar e transferred. so transfer is performed twice busy flag outputs "high" after the second transfer are ended. an example of timing sequence is shown below. rs r/w e internal signal db7 internal operation d7 busy ac3 no busy instruction busy flag check instruction busy flag check d3 ac3 d7 d3 figure 5. example of 4 - bit bus mode timing diagram
S6A0071 32com/60seg driver & controller for dot matrix lcd 18 application informat io n according to lcd p anel 1) lcd panel: 24 character 1 - line character format: 5 7 dots + 1 cursor line (1/5 bias, 1/16 duty) S6A0071 com1 com7 com8 seg1 seg10 seg60 com16 com10 com2 com3 com4 com5 com6 seg2 seg3 seg4 seg5 seg6 seg7 seg8 seg9 seg59 seg58 . . com15 com14 com13 com12 com11 com9
32com/60seg driver & controller for dot matrix lcd S6A0071 19 2) lcd panel: 24 character 2 - line character format: 5 7 dots + 1 cursor line (1/6.7 bias, 1/3 2 duty) S6A0071 com1 com7 seg1 seg60 com32 . . com17 com23 com24 com2 com3 com4 com5 com6 com8 com18 com19 com20 com21 com22 seg2 seg3 seg4 seg5 seg58 seg59 com31 com30 com29 com28 com27 com26 com25 com16 com15 com14 com13 com12 com11 com10 com9
S6A0071 32com/60seg driver & controller for dot matrix lcd 20 power supply for dri ving lcd panel 1) when an external power supply is used vdd v1 v2 v3 v4 v5 vdd r r r0 r r vee v5out vss c1 c2 open open 2) when an internal booster is used (boosting twice) vdd v1 v2 v3 v4 v5 r r r0 r r v5out vss c1 c2 vci + - + - + - vdd vr 4.7 m f 4.7 m f 4.7 m f vdd v1 v2 v3 v4 v5 r r r0 r r v5out vss c1 c2 vci + - + - + - vdd 4.7 m f 4.7 m f 4.7 m f vr vr: contrast control resistor notes: 1. boosted out put voltage should not exceed the maximum value (11v) of the lcd driving voltage. 2. a voltage of over 5.5v should not be input into the reference voltage (vci) when boosting twice. 3. the value of resistance, according to the number of lines, duty ratio and the bias, is shown below. (refer to table 8)
32com/60seg driver & controller for dot matrix lcd S6A0071 21 table 8. duty ratio and power supply for lcd driving item data number 1 2 duty ratio 1/16 1/32 bias 1/5 1/6.7 divided r r r resistance r0 r 2.7r initializing when the power is turned on, S6A0071 is initialized automatically by power on reset circuit. during the initialization, the following instructions are executed, and bf(busy flag) is kept "high"(busy state) to the end of initialization. (1) display clear instruction: write "20h" to all ddram (2) set functions instruction dl = 1 : 8 - bit bus mode n = 1 : 2 - line display mode (3) control display on/off instruction d = 0 : display off c = 0 : cursor off b = 0 : blink off (4) set entry mode instruction i/d = 1 : increment by 1 sh = 0 : no entire dis play shift
S6A0071 32com/60seg driver & controller for dot matrix lcd 22 frame frequency b - type waveform (frame inversion) 1) 1/16 d uty c ycle vdd v1 v4 v5 . . com1 1 frame 1 frame 1-line selection period ... ... 16 15 3 2 1 16 15 4 3 2 1 item clock/frequency 1 - line selection period 120 clocks frame frequency 140.7hz * f osc = 270khz (1 clock = 3.7 m s) 2) 1/32 duty cycle vdd v1 v4 v5 . . com1 1 frame 1 frame 1-line selection period ... ... 32 31 3 2 1 32 31 4 3 2 1 item clock/frequency line selection period 120 clocks frame frequency 70.4hz * f osc = 270khz (1 clock = 3.7 m s)
32com/60seg driver & controller for dot matrix lcd S6A0071 23 initializing by inst ruction 1) 8 - bit interface mode power on wait for more than 20ms after v dd rises to 4.5v wait for more than 30ms after vdd rises to 2.7v rs r/w db7 db6 db5 db4 db3 db2 db1 db0 function set 0 0 0 0 1 dl(1) n x x x wait for more than 39 m s rs r/w db7 db6 db5 db4 db3 db2 db1 db0 display on/off control 0 0 0 0 0 0 1 d c b wait for more than 39 m s rs r/w db7 db6 db5 db4 db3 db2 db1 db0 display clear 0 0 0 0 0 0 0 0 0 1 wait for more than 1.53 ms rs r/w db7 db6 db5 db4 db3 db2 db1 db0 entry mode set 0 0 0 0 0 0 0 1 i/d sh initialization end dl 0 1 1-line mode 2-line mode n 0 1 4-bit interface 8-bit interface d 0 1 display off display on c 0 1 cursor off cursor on b 0 1 blink off blink on i/d 0 1 decrement mode increment mode sh 0 1 entire shift off entire shift on condition: fosc = 270khz
S6A0071 32com/60seg driver & controller for dot matrix lcd 24 2) 4 - bit interface mode power on wait for more than 20ms after v dd rises to 4.5v wait for more than 30ms after v dd rises to 2.7v rs r/w db7 db6 db5 db4 db3 db2 db1 db0 function set 0 0 0 0 1 dl(0) x x x x wait for more than 39 m s rs r/w db7 db6 db5 db4 db3 db2 db1 db0 display on/off control wait for more than 39 m s rs r/w db7 db6 db5 db4 db3 db2 db1 db0 clear display wait for more than 1.53 ms rs r/w db7 db6 db5 db4 db3 db2 db1 db0 entry mode set initialization end dl 0 1 1-line mode 2-line mode f 0 1 4-bit interface d 0 1 display off display on c 0 1 cursor off cursor on b 0 1 blink off blink on i/d 0 1 decrement mode increment mode sh 0 1 entire shift off entire shift on 0 0 0 0 0 0 x x x x 0 0 1 d c b x x x x 0 0 0 0 0 0 x x x x 0 0 0 1 i/d sh x x x x 0 0 0 0 0 0 x x x x 0 0 0 0 0 1 x x x x condition: fosc = 270khz rs r/w db7 db6 db5 db4 db3 db2 db1 db0 function set 0 0 0 0 1 0 x x x x 0 0 n x x x x x x x wait for more than 39 m s 8-bit interface
32com/60seg driver & controller for dot matrix lcd S6A0071 25 maximum absolute lim it rating maximum absolute power ratings description symbol unit value power supply voltage (1) v dd v - 0.3 to +7.0 lcd drive voltage v lcd v v dd - 13.5 to v dd +3.0 input voltage v in v - 0.3 to v dd +0.3 note: voltage gre ater than above may damage the circuit. (v dd 3 v1 3 2 3 v3 3 v4 3 v5) temperature characteristics description symbol unit value operating temperature t opr c - 3.0 to +85 storage temperature t stg c - 5 5 to +125
S6A0071 32com/60seg driver & controller for dot matrix lcd 26 electrical character istics dc charact eristics ( v dd = +5v 10%, ta = - 30 to +85 c) characteristic symbol condition min typ max unit operating voltage v dd - 4.5 5.0 5.5 v supply current i dd internal oscillation or external clock operation. (v dd = 5v, f osc = 270 khz) - 0.6 1.0 ma input vol tage (1) v ih1 - 2.3 - v dd (except osc1) v il1 - - - 0.8 v input voltage (2) v ih2 - v dd - 1.0 - v dd (osc1) v il2 - - - 1.0 v output voltage (1) v oh1 i oh = - 0.205ma 2.4 - - (db0 to db7) v ol1 i ol = 1.6ma - - 0.4 v output voltage (2) v oh2 i o = - 40 m a 0.9v dd - - (osc2) v ol2 i o = 40 m a - - 0.1v dd v voltage drop vd com - - 1 vd seg i o = 0.1ma - - 1 v input leakage current (1) e i il1 v in = 0v to v dd - 1 - 1 input leakage current(2) (r/w, rs, db0 to db7) i il2 v in = v dd - 5 - 5 low input curren t (r/w, rs, db0 to db7) i in v in = 0v, v dd = 5v (pull up) - 50 - 125 - 250 m a internal clock (external rf) f ic rf = 91k w 2% (v dd = 5v) 190 270 350 f ec 160 250 350 khz external clock duty - 45 50 55 % t r , t f - - 0.2 m s v5out iout = 1ma, ta = 25 c - 4 .5 - 4.7 - v voltage doubler v ef r l = 95 99.9 - % vci input voltage 2.5 - 5.5 v lcd driving voltage v lcd v dd - v 5 (1/5, 1/6.7 bias) 3.0 - 13.5 v
32com/60seg driver & controller for dot matrix lcd S6A0071 27 dc characteristics (v dd = + 3 v 20%, ta = - 30 to +85 c) characteristic symbol condition min typ max uni t operating voltage v dd - 2.4 3.0 3.6 v supply current i dd internal oscillation or external clock. (v dd = 3v, f osc = 270khz) - 0.2 0.3 ma input voltage (1) v ih1 - 0.8v dd - v dd (except osc1) v il1 - - - 0.2v dd v input voltage (2) v ih2 - v dd - 1.0 - v dd (osc1) v il2 - - - 1.0 v output voltage (1) v oh1 i oh = - 0.205ma 2.0 - - (db0 to db7) v ol1 i ol = 1.6ma - - 0.5 v output voltage (2) v oh2 i o = - 40 m a 0.9v dd - - (osc2) v ol2 i o = 40 m a - - 0.1v dd v voltage drop vd com - - 1 vd seg i o = 0.1ma - - 1 v input leakage current (1) e i il1 v in = 0v to v dd - 1 - 1 input leakage current(2) (r/w, rs, db0 to db7) i il2 v in = v dd - 5 - 5 low input current (r/w, rs, db0 to db7) i in v in = 0v, v dd = 3v (pull up) - 10 - 25 - 50 m a internal clock (external rf) f ic rf = 91k w 2% (v dd = 3v) 160 240 320 khz v5out iout = 1ma, ta = 25 c - 2.5 - 2.75 - v voltage doubler v ef r l = 95 99.9 - % vci input voltage 1.8 - v dd v lcd driving voltage v lcd v dd - v 5 (1/5, 1/6.7 bias) 3.0 - 12.0 v
S6A0071 32com/60seg driver & controller for dot matrix lcd 28 ac characteristics (v dd = 4 .5 to 5.5v, ta = - 30 to +85 c ) mode characteristic symbol min typ max unit e cycle time t c 500 - - e rise time / fall time t r , t f - 20 e pulse width ( high, low ) t w 220 - - r/w and rs setup t ime t su1 40 - - r/w and rs hold time t h 1 10 - - data setup time t su2 60 - - write mode (refer to figure 6) data hold time t h 2 10 - - ns e cycle time t c 500 - - e rise time / fall time t r , t f - 20 e pulse width ( high, lo w ) t w 220 - - r/w and rs setup time t su 40 - - r/w and rs hold time t h 10 - - data output delay time t d - - 120 read mode (refer to figure 7) data hold time t dh 10 - - ns ac characteristics (v dd = 2 . 4 to 3 . 6 v, ta = - 30 to +85 c ) mode characteristic symbol min typ max unit e cycle time t c 14 00 - - e rise time / fall time t r , t f - 20 e pulse width ( high, low ) t w 50 0 - - r/w and rs setup time t su1 7 0 - - ns r/w and rs hold time t h 1 10 - - data setup time t su2 195 - - write mode (refer to figure 6) data hold time t h 2 10 - - e cycle time t c 14 00 - - e rise time / fall time t r , t f - - 20 e pulse width ( high, low ) t w 50 0 - - ns r/w and rs setup time t su 70 - - r/w and rs hold t ime t h 10 - - data output delay time t d - - 60 0 read mode (refer to figure 7) data hold time t dh 2 0 - -
32com/60seg driver & controller for dot matrix lcd S6A0071 29 v ih1 v il1 t su1 v il1 t h1 v il1 t h1 t f t w t h2 v ih1 v il1 t su2 t r v ih1 v il1 valid data v ih1 v il1 t c db0 - db7 e r/w rs v il1 v ih1 v il1 figure 6. write mode timing diagram v ih1 v il1 t su v ih1 t h v ih1 t h1 t f t w t dh v ih1 v il1 t r v oh1 v ol1 valid data v oh1 v ol1 t c db0 - db7 e r/w rs t d v il1 v ih1 v il1 figure 7. read mode timing diagram

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